As a core IP that accounts for ‌20%-60%‌ of the total chip area in chip design, the selection of Memory  Compiler directly determines the chip's area, performance, power consumption  and tape-out cost. Since the 40nm process node, with the exponential  improvement of chip integration, the categories of Memory Compilers have  rapidly diversified, and products with different architectures, ports and  memory cells show significant differences. Understanding their physical essence  beyond superficial types to make the optimal selection has become core knowledge  for chip design teams across the industry.
With 8 years of in-depth experience in Foundation IP R&D and  mass production, Suzhou IPSOAR Microelectronics has built a full-process node  product matrix covering Planar and FinFET processes. Based on the mission of  coordinated industrial development, IPSOAR officially launched the  "Foundation IP In-depth Usage Popularization Program" on its 8th  anniversary. This article breaks down the classification logic, features and  selection pitfalls of Memory Compilers from the physical layer, providing  professional and practical technical references for the industry to help  improve chip design efficiency.
1. Core Dimension 1: Port Architecture — Defining the Basic Working  Mode of Memory‌
 Port is the most essential classification basis for Memory  Compilers. Different port configurations correspond to distinct clock  mechanisms, read-write parallelism and Bit Cell structures, making it the  primary judgment criterion for selection.

Port Type	Clock Count‌	Read-Write Port‌	memory cell	Schematic Diagram of Memory Cell Structure	Core Physical Characteristics‌
Single Port    (SP)	1	1 rw	6T		Simplest structure, smallest area, lowest power consumption, supporting only read or write operations at the same moment
Two Port    (2P)	2	1 r +    1 w	8T	Or	Support simultaneous read-write parallel  operations‌
Dual Port    (DP)	2	1 rw + 1rw	8T		Support bidirectional read-write parallel operations
Pseudo Two Port    (UHD 2P）	1	1 r + 1w	6T		Implement Two-Port functionality under a single clock with a smaller area‌
ROM	1	1 r	1T		Ultra-compact unit area, non-modifiable fixed data, highest reliability‌

Core Conclusion: The  number of ports directly determines the concurrency capability of the memory,  and is positively correlated with area and power consumption. The pseudo  two-port design performs read and write operations in a time-sharing manner  internally under a single clock, enabling the reuse of 6T cells to achieve the  optimal balance between functionality and cost.‌ ‌

2. Core Dimension 2:  Architecture Type — Capacity Adaptation Logic of Register File and SRAM‌
 Under the same port configuration, Register File and  SRAM are the two mainstream architectures, and their core differences stem from  their completely different order-of-magnitude capacity ranges.

Taking IPSOAR's 22nm  process, 128Kbit Memory data as an example, the 1P RF is 13% smaller in area  than the SP SRAM：

Selection Tip: For small-capacity scenarios, prioritize Register File. It  can save approximately 10%~20% of the chip area without affecting the digital  design flow.‌ ‌

3. Core Dimension 3: Performance Grade — Design  Priority Differences of HD/UHD/HS‌
 The industry's widely used naming conventions HD  (High Density), UHD/EHD (Ultra High Density), and HS (High Speed) are  essentially design-oriented distinctions based on memory cell dimensions,  corresponding to the two core demands of "area priority" and  "speed priority" respectively.

Taking IPSOAR's 22nm process, 512Kbit single-port  product as an example, the quantitative comparison of area and timing is as  follows:

Key Reminder: Some processes or vendors use HD/HS  as their product series, while others use UHD/HD as their series.
4.  Comprehensive Analysis of 22nm Process Memory Compiler Types‌
 Based on the full range of IPSOAR's 22nm Memory Compiler types, the  distinctions of each type are introduced as follows:

For the high-demand specification of 22nm 16Kbit  dual-port, a targeted comparison of area and timing differences is as follows:‌

Selection Conclusion:‌  UHD 2P SRAM can save ‌45%‌ of the area, but with a ‌20%‌ increase in timing  delay. It is suitable for designs that do not require extremely high speed but  pursue ultimate area and cost optimization.
5. Pitfall Avoidance  Guide: Common Industry Selection Misunderstandings and Professional  Explanations‌
Based on usage feedback from  serving over 100 chip design clients, IPSOAR has summarized the four most  common selection pitfalls to help the industry avoid design rework and cost  waste.
‌Misunderstanding 1:  Single Port Memory only needs SRAM, not Register File (RF).‌
 ‌Professional  Explanation:‌ The two are fully compatible at the digital  design interface level with no usage differences, but capacity is the core  dividing point. For small capacities, Register File's area is ‌15%-25%‌ smaller than  SRAM of the same specification, with better timing. Prioritizing RF can  directly reduce chip area and lower chip cost.
‌Misunderstanding 2:  When timing is tight, simply replace the HD series with the HS series.‌
 ‌Professional  Explanation:‌ The HS series improves speed by selecting  larger memory cell sizes and design optimizations, typically being ‌10%-30%‌ faster than  the HD series. However, attention must be paid to process cost differences: HS  products using large Bit Cells may require confirmation with the wafer foundry  regarding the need for ‌2 additional metal mask layers‌. Otherwise,  overall manufacturing costs could increase by approximately ‌5%‌. Selection  requires comprehensive consideration of timing margin, area constraints, and  wafer cost.
‌Misunderstanding  3: When selecting Two Port memory, seeing HD 2P and UHD 2P but not knowing the  difference.‌
 ‌Professional  Explanation:‌ In advanced processes, there are two types  of Two Port Memory. Focus on two indicators when choosing: one is the number of  clocks (if 2 clocks, it's standard Two Port; if 1 clock, it's Pseudo Two Port  or UHD 2P); the other is the Bit cell (if it's an 8T bit cell, it's standard  Two Port; if it's a 6T bit cell, it's Pseudo Two Port or UHD 2P).
‌Misunderstanding  4: Comparing Memory compilers from different companies, finding that Company  A's SP memory area is smaller than Company B's, and thus choosing Company A's  MC.‌
 ‌Professional  Explanation:‌ There are many types of SP memory, and  naming conventions vary between companies (e.g., HD 1P RF/HD SP SRAM/UHD 1P  RF/UHD SP SRAM/HS 1P RF/HS SP SRAM). When comparing, the first step is to check  whether it is a register file or SRAM. The second step is to see which series  (UHD/HD/HS) it belongs to—essentially, looking at the SRAM bit cell size is  sufficient. The third step is to check the maximum supported capacity. If  comparing only at medium capacity, Company A's area might be smaller than  Company B's, but if Company A does not support large capacities while Company B  does, then for larger capacities, Company B might only need one instance,  whereas Company A requires multiple instances stitched together. In this case,  Company B's MC might actually occupy less area on the chip than Company A's.  Taking 22nm as an example:

6. IPSOAR Microelectronics: Crafting High-Quality  IP with Dedication, Fulfilling the Mission, Serving as a Knowledge Disseminator  in the  Foundation IP Industry‌
As a benchmark enterprise in China focused on  Foundation IP R&D and mass production, Suzhou IPSOAR Microelectronics  adheres to its original intention of quality, deeply optimizes PPA (Power,  Performance, Area) around the characteristics of each process platform, and  provides customers with highly competitive Foundation IP solutions. The  company's independently developed Memory IP has served ‌14 Foundries‌, covering  mainstream process nodes including 0.18um, 0.11um, 90nm, 55nm, 40nm, 28nm,  22nm, and FinFET. Process Features cover logic, HV, BCD, BSI, CIS, Eflash, Auto  Grade 1, etc., widely used in consumer electronics, automotive electronics,  artificial intelligence, industrial control, and other fields.
Zhou Bin, COO of IPSOAR, stated: "Memory  Compiler IP is a crucial core module in ASIC/SoC chips. Due to its complex  technical system, we have found in serving customers that many teams have  insufficient understanding of the characteristics of various memory compilers,  making it difficult to achieve reasonable selection and efficient application.  As the local enterprise with the highest market share in the  Foundry shelf Foundation IP market, IPSOAR  Microelectronics is not only committed to providing customers with high-quality  IP products but also hopes to help industry partners use the products well and  maximize IP value. Therefore, we will also proactively shoulder the  responsibility, act as the industry's Chief Knowledge Officer, and continuously  output professional technical content." ‌

【About IPSOAR】
 Suzhou IPSoar Microelectronics Co., Ltd. (founded  in 2018, headquartered in Suzhou) is a leading one-stop Foundation IP and  Memory IP supplier in China, specializing in providing high-reliability,  high-PPA competitive IP solutions. Its product line comprehensively covers core  IPs such as Memory Compiler, Standard Cell Library, GPIO, TCAM Compiler, and  OTP, supporting process nodes from 0.18μm to 22nm and advanced process  platforms.
As an officially certified partner of 14  mainstream  Foundries, the company not  only ranks among the few manufacturers capable of providing full-chain IP  support from mature processes to advanced nodes but has also been honored with  outstanding supplier awards from multiple Foundries due to its stable delivery  capabilities and high-quality Foundation IP products and services. In 40nm/28nm  and advanced nodes, the PPA (Power/Performance/Area) metrics of its IP products  are 5%-20% better than the industry average. The company focuses on the  reliability of Foundation IP, relying on a comprehensive quality inspection  process. It has now passed ISO 9001 quality system certification, ISO 27001  information security certification, and ISO 26262 functional safety management  system ASIL D certification, ensuring a 100% tape-out success rate.