Body: Recently, Suzhou IPSoar Microelectronics Co., Ltd. (hereinafter referred to as "IPSoar"), a leading one-stop Foundation IP supplier in China, announced the successful R&D and launch of the country's first Memory Compiler IP based on the 40nm ULP eFlash process. This product is specifically tailored for the 40nm ULP eFlash process, having completed chip testing and validation, and passed the stringent qualification certification of mainstream foundries. It is the first officially qualified Memory Compiler product for this process node, providing a high-competitiveness and high-reliability foundational IP for domestic MCU chip design enterprises.

1. Product Advantages: Focused on Core Application Scenarios, Deep Optimization of PPA Metrics

As a core component of MCU chips, the Memory Compiler directly determines the chip's storage performance, power consumption control, and cost optimization. Its technical maturity and process compatibility are key to the mass production and application of MCU products. The platform's first 40nm ULP eFlash Memory Compiler launched by IPSoar  focuses on the application requirements of core scenarios such as industrial control, consumer electronics, and the Internet of Things. It achieves deep optimization in the three key indicators of power consumption, performance, and area (PPA), not only enhancing the competitiveness of this platform but also providing a high-reliability, high-yield IP.

2. Technological Innovation: Extreme Area Optimization, Outstanding Low-Power Performance, High Reliability and High Yield Assurance

This IP achieves three core advantages through full-customized design and deep process adaptation:

Extreme Area Optimization: Relying on IPSoar's precise control over the characteristics of the 40nm ULP eFlash process, it adopts innovative storage architecture and optimization iteration schemes. The chip area is optimized by 5%-15% compared to industry peers, significantly reducing the overall cost of MCU chips.

Outstanding Low-Power Performance: Based on the foundry's ultra-low-power bit cell and combined with the company's proprietary static and dynamic power management technologies, it reduces static power consumption by 15%-30% while meeting high-speed read/write requirements, perfectly adapting to the stringent power requirements of IoT devices and portable terminals.

High Reliability and High Yield Assurance: After full-process IP validation and chip tape-out validation, the product's yield and stability reach international mainstream levels, directly meeting the demands of complex application scenarios such as industrial-grade high temperature and long lifespan.

Collaborative Innovation, Shared Future

"We are honored to launch the country's first Memory Compiler IP based on the 40nm ULP eFlash process, filling the gap in the lack of an optimal memory compiler for this process platform. This IP is another iteration upgrade in our 40nm technology, tailoredly optimized for the characteristics of the 40nm ULP eFlash process and the competitiveness of MCU chips," said Zhou Bin, Co-founder and COO of IPSoar. "The landing of this product is another practice of our mission to 'empower customer innovation with high-quality Foundation IP'—by deeply adapting to the process and optimizing core indicators, we help domestic MCU enterprises enhance their product competitiveness. This IP has been adopted by a large number of leading MCU companies. In the future, the company will continue to deepen collaborative innovation with foundries and chip design enterprises, improve the full-node IP product matrix, and co-build an autonomous and controllable semiconductor industry ecosystem, providing a 'chip power' foundation for enhancing the competitiveness of Chinese chips."

About IPSoar:

Suzhou IPSoar Microelectronics Co., Ltd. (founded in 2018, headquartered in Suzhou) is a leading one-stop Foundation IP and Memory IP supplier in China, specializing in providing high-reliability, high-PPA competitive IP solutions. Its product line comprehensively covers core IPs such as Memory Compiler, Standard Cell Library, GPIO, TCAM Compiler, and OTP, supporting process nodes from 0.18μm to 28nm and advanced process platforms.

As an officially certified partner of 12 mainstream domestic Foundries, the company not only ranks among the few manufacturers capable of providing full-chain IP support from mature processes to advanced nodes but has also been honored with outstanding supplier awards from multiple Foundries due to its stable delivery capabilities and high-quality Foundation IP products and services. In 40nm/28nm and advanced nodes, the PPA (Power/Performance/Area) metrics of its IP products are 5%-20% better than the industry average. The company focuses on the reliability of Foundation IP, relying on a comprehensive quality inspection process. It has now passed ISO 9001 quality system certification, ISO 27001 information security certification, and ISO 26262 functional safety management system ASIL D certification, ensuring a 100% tape-out success rate.

IPSoar consistently adheres to the mission of "Empowering Customers with High-Quality Foundation IP." Through continuous technological iteration and customer collaboration, it helps partners achieve full-cycle value enhancement from IP selection and chip design innovation to successful mass production.

Company Email: sales@ipsoar-tech.com

Company Website: www.ipsoar-tech.com